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CALL FOR PAPERS - Summary,Plenary Talk, and Area scope -
Area 3
CMOS Devices / Device Physics |
| (Chair: K. Shibahara, Hiroshima Univ.) |
The aim of this area is to discuss advanced silicon device technologies and physics. Papers are solicited in the following areas: (1) sub-100-nm silicon CMOS devices and their integration technologies; (2) performance enhancement technologies, such as a strained-silicon channel and SiGe and Ge channels; (3) post-bulk-planar silicon device structures, including planar SOI, FinFET, and double gate FET; (4) device physics of advanced CMOS, including simulation and modeling on carrier transport and reliability; and (5) manufacturing and yield science.
Invited Speakers:
“Progress in Technology Oriented Analytical Modeling of Advanced Quasi Ballistic Ultra Thin Body MOSFETs” |
| R. Clerc (IMEP, France) |
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| “LSTP/LOP CMOS Process Integration Scheme for 45-32 nm node” |
| K. Imai (NEC, Japan) |
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| “Impact of RTS on Vth Fluctuation (tentative)” |
| A. S. Spinelli (Politecnico di Milano, Italy) |
Area 4
Advanced Memory Technology |
| (Chair: A. Nitayama, Toshiba) |
Advanced memory technologies are very much expected to explosively evolve SoC devices and digital information technologies toward ‘‘high speed and high density, broadband and mobile.’’ Papers are solicited in the area of all advanced volatile or nonvolatile memory devices, such as DRAM, flash (including SONOS and nanocrystal devices), FeRAM, MRAM, phase change RAM, resistance RAM, one time programming memory, 3-D memory, and others. Topics include cell device physics and characterization, process integration and materials, tunneling dielectrics, ferroelectric and ferromagnetic materials, reliability, failure analysis, quality assurance and testing, modeling and simulation, process control and yield enhancement, integrated circuits, new concept memories, and new applications and systems (solid state disks, memory cards, programmable logic, etc.).
Invited Speakers:
“Current Development Status and Future Challenge of Transition Metal Oxide ReRAM Technologies” |
| N. Awaya (Sharp, Japan) |
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| “Current Development Status and Future Challenge of 3D Stacked NAND Flash Technologies” |
| S. M. Jung (Samsung Electronics, Korea) |
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| “Status and Future Challenge of Manufacturable PRAM Technologies” |
| Y. Matsui (Hitachi, Japan) |
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| “Overview and Future Challenge of Floating Body Cell Technologies” |
| T. Shino (Toshiba, Japan) |
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