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CALL FOR PAPERS - Summary,Plenary Talk, and Area scope -
2007 INTERNATIONAL CONFERENCE ON
SOLID STATE DEVICES AND MATERIALS
Conference: September 19-21, 2007
Short Course (in Japanese): September 18, 2007
The 2007 International Conference on Solid State Devices and Materials (SSDM2007) will be held from September 19 to September 21, 2007 at Tsukuba International Congress Center (Tsukuba, Ibaraki, Japan). Since 1969, the conference has provided an excellent opportunity to discuss key aspects of solid-state devices and materials. For the 2007 conference, 13 program subcommittees have been organized covering circuits and systems, as well as devices and materials. A one-day short course is also scheduled prior to the conference, offering tutorial lectures on important aspects of the technology.
Original, unpublished papers will be accepted after review by the Program Committee. Several invited speakers will cover topics of current interest. An Advance Program will appear in July. More information about SSDM2007 is available online at:
http://www. ssdm.jp
PLENARY SESSIONS
Plenary Speakers:
“New Technology: Silicon Photonics: Opportunity, Challenges & Applications” |
M. Paniccia (Intel, USA) |
“Organic Transistors: Towards Ambient Electronics” |
T. Someya (The Univ. of Tokyo, Japan) |
SCOPE OF CONFERENCE
The conference aims at providing a forum for synergistic interactions among research scientists and engineers working in the fields related to solid state devices and materials and encouraging them to discuss problems to be solved in these fields, new findings, new phenomena, and state-of-the-art technologies related to devices and materials. The conference also aims to facilitate mutual understanding among people in the device and material fields and those in the circuit, system and packaging fields. For the 2007 conference, thirteen program subcommittees have been organized in order to realize selection of higher quality papers and strengthen specific technology areas. The scope of each subcommittee is listed below.
Area 1
Advanced Gate Stack / Si Processing Science |
(Chair: Y. Nara, Selete) |
This subcommittee covers all the innovative front-end-ofline process technologies and sciences for advanced silicon-based LSI devices. Not only the gate stack technology but all the new concepts on Si-based front-end process technologies are welcome. Papers are solicited in the following areas (but are not limited to these areas):(1) advanced gate stack technologies, such as a SiON gate insulator, high-k gate insulator, and metal gate technologies, including device integration technology;(2) front-end-of-line process technologies that break through the scaling limit, such as a low-temperature process, shallow junction formation, novel diffusion/oxidation, and high-precision etching; (3) reliability physics and analysis; and (4) characterization and modeling of a Si process.
Invited Speakers:
“Schottky Barrier and Stability of Metal/high-k Interfaces: Theoretical View” |
T. Nakayama (Chiba Univ., Japan) |
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“Study of Dopant Diffusion and Defect Evolution for Advanced Ultra Shallow Junctions based on an Atomistic Modeling” |
T. Noda (Matsushita, IMEC, Belgium) |
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“Solutions and Challenges for High-k/Metal Gate CMOS” |
J. Schaeffer (Freescale, USA) |
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“NBTI and PBTI in High k/ metal FETs” |
S. Zafar (IBM, USA) |
Area 2
Characterization and Materials Engineering for Interconnect Integration |
(Chair: S. Ogawa, Selete) |
Technologies and sciences that cover a Si back-end-ofline process are discussed, including package technology. Low-k materials have been in practical use; however, they brought new, difficult issues with decreasing in size, especially in reliability and package areas, and these areas require different ideas from conventional interconnect in characterization, material, and process/structure technologies. Papers are solicited in the following areas(but are not limited to these areas): (1) characterization methodology for materials, mechanical and electrical properties in small geometry, metrology and yield improvement; (2) materials and process technologies for advanced Cu/Low-k interconnect, including new dielectric and metal formation, planarization, and etching;(3) reliability phenomena and physics, such as EM, SIV, TDDB, and modeling/prediction; (4) Passive components for RF or High-speed operations; (5) packaging for Cu/Low-k chips; (6) new concepts and materials for future interconnects, such as a 3-D structure, a CNT interconnect, and wireless applications. A special session focused on advanced Cu/Low-k technologies is scheduled to highlight this area through unit processes, characterization, up to reliability.
Invited speakers will be informed. |
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