Awards

There are four categories of awards for authors who presented distinguished papers at SSDM.

SSDM Award

The SSDM Award is awarded to authors who contributed an outstanding paper at past SSDM.

The paper demonstrated vertical trench gates formed by anisotropic dry etching for Si power MOSFETs and proved its effectiveness in improving integration capability and high performance. Their demonstration showed that the dry etching improves integration density of channels with the advantageous crystal plane for MOSFET, thereby reducing on-resistance. Trench MOSFET is now the most commonly used transistor in power devices and has been driving electrical power savings.

In the silicon semiconductor manufacturing process, trench-forming technology using wet etching first appeared in the 1960s. Relevant applications were enthusiastically considered into the 1970s. Among these, trench gates were actively considered for use in the power device field because it was clear that they could improve current drivability. Wet etching takes advantage of the difference in etching rate depending on the crystal plane, so a device with a V-shaped trench called VMOS was initially developed. With this structure, the electric field concentrated at the tip of the V, causing problems such as break down of the gate insulating film. To address this issue, a structure called UMOS was proposed, in which the orientation of the substrate crystal was changed to form a rectangular groove, but this required the use of crystal planes that were unsuitable for use as MOSFET channels.

This paper demonstrated that high integration could be realized by switching from wet etching to dry etching, which does not depend upon crystal orientation, to form the grooves. It also revealed a method for eliminating damage from etched channel surfaces, which was a major concern with dry etching. Moreover, although not mentioned in the paper, the authors have shown in a patent filed prior to this paper and in a subsequent paper that preferred crystal orientation can be utilized in MOSFET channels. These technologies realized a trench power MOS with the world's lowest on-resistance at the time.

Based on this paper, technology has been widely applied in the power device field that uses the sidewalls of trenches formed with dry etching for channels. Trench gates have become an essential structure of not only power MOS, but also Insulating Gate Bipolar Transistors (IGBT), which are currently widely used in power devices, as well as SiC power MOS, which have started to be commercially used in recent years.

In comparison to power devices for which a three-dimensional structure has actively been incorporated, logic devices have been scaled longer to maintain their planer structure. Nevertheless, since the 2010 decade when scaling reached its limits, a three-dimensional structure has been used that is known as FIN channel which uses the sidewalls formed with dry etching. Consequently, this paper can be seen as one of the origins of three-dimensional devices.

In recognition of how this paper paved the way for three-dimensional devices that are a core pillar of today’s semiconductor industry and made a tremendous contribution to academia as described above, this SSDM Award is presented in honor of those achievements.

• 

  Daisuke Ueda

  National Yang Ming Chiao Tung University
  (Education)

  Sept. 1987	Ph.D.	Osaka University
  Mar. 1979	M.S.	Kyushu Institute of Technology
  Mar. 1977	B.S.	Kyushu Institute of Technology

  (Academia)

  2016 - now	Visiting Professor, National Yang Ming Chiao Tung University, Taiwan
  2019 - 2023	Specially Appointed Professor, Nagoya University, Japan
  2014 - 2019	Specially Appointed Professor, Green Innovation Center

  (Industry)

  2007 - 2014	Executive Director of Advanced Research Laboratories, and Principal Engineer, Director of Device Solution Center, Director of Nanotechnology Laboratory, and Director of Information & Intelligence Research Laboratory, Panasonic
  2002 - 2007	Director of Semiconductor Device Research Center, Matsushita Electronics Corp.

  (Award)

  June. 2023	Hall of Fame, IEEE ISPSD
  Sept. 2016	Fellow, JSAP (Japan Society of Applied Physics)
  Dec. 2008	Fellow, IEEE
  Sept. 2007	Fellow, IEICE
  Dec. 2007	ELEX Best Paper Award, IEICE
  Mar. 2001	Okochi Memorial Production Award 2001
  Feb. 1998	Best Panelist Award, IEEE ISSCC 1997
  Mar. 1996	Okochi Memorial Technology Award 1996

  (Societies)

  2011 - 2012	Program Committee Chair, SSDM (Slid-state Device & Materials)
  2004 - 2005	Chair, EDS Kansai Chapter, IEEE
  2001 - 2003	Vice Chair, Electronics Society, IEICE
  1999 - 2001	Chair, Electronic Devices Research Workshop, IEICE
  1998 - 2003	Editor, EDL (Electron Device Letters), IEEE
  1998 - 2000	Organizing/Program Committee Chair, TWHM

• Hiromitsu Takagi

• Akio Shimano

• 

  Gota Kano

  Symetrix Corporation

  Professor Emeritus, Kochi University of Technology, Visiting Professor, Kyoto Institute of Technology and a Member of Borad, Symetrix Corporation (USA), IEEE Life Fellow.
  Since he received BS (1961) and Ph.D. (1970) from Osaka University, his major works were served at Panasonic Corporation where he became a Member of Board MEC, Managing Director in charge of the Electronics Research Laboratory. After he retired from Panasonic in 1998, he experienced several Professors and Consultants in Japan as well as in the US and China.
  Throughout his active career, Dr. Kano has received many awards, holds more than 130 patents, has published more than 90 presentations, has presented at 30 international conferences, and has published 5 books.
  With his rigid philosophy of applying an entrepreneurial spirit while simultaneously making profits and achieving business goals, he has established himself as an innovative thinker who hopes to create as much value for the future generation.

History of the SSDM Award is here

SSDM Paper Award (PA)

SSDM Paper Award is awarded to the best paper presented at the previous year’s SSDM.

• 

  Curtis S Durfee

  IBM Research

  Curtis Durfee received a PhD degree in Physics from the University of Illinois at Urbana-Champaign in 2001, studying rare-earth thin film magnetostrictive phase transitions. In 2001, he joined Intel as an epitaxial process engineer and supported the insertion of strained silicon transistors into the 90nm node and development across 5 subsequent technology nodes. He currently works with IBM Research developing gate-all-around nanosheet technology with a focus on epitaxy and selective dry etch processes. He has authored or co-authored over 30 papers in scientific journals and conference proceedings.

• 

  Ivo Victor Otto IV

  TEL Technology Center

  Ivo Otto IV received his M.S. in Nanoscale Engineering from the University at Albany in 2023 and is currently a Nanoscale Engineering PhD. candidate under Professor Christophe Valleé, at the University of Albany. His thesis work focuses on development of plasma etching processes for removal of BEOL liner materials, such as TaN, with high selectivity to SiOCH low-κ films by coupling selective deposition and etching regimes. Ivo has worked at the TEL Technology Center of America, in Albany, NY, within the Certas Etch Systems group for five years. His work has focused on highly selective, gas-phase etch applications for gate-all-around nanosheet technologies and emerging stacked FET integrations where isotropic etch modules are becoming more prevalent.

• 

  Subhadeep Kal

  TEL Technology Center

  Subhadeep received his Ph.D degree from Rensselaer Polytechnic Institute at Troy, NY, in 2013. He has been with TEL for 10 years, working on dry etch solutions for advanced logic nodes. He is currently a member of technical staff at TEL. He has authored more than 50 papers and patents throughout his career, and has received more than 500 citations.

• 

  Shanti Pancharatnam

  IBM Research

  Shanti graduated with a M.S in Nanoscale Engineering from SUNY-CNSE, Albany in 2013, and joined IBM in 2014. She has since owned several key FEOL tools and processes for high-k, metal gate, tungsten deposition, and dry etch. Her contributions have had broad impact across programs and led to improved dry etch processes for the critical modules in nanosheet technology and enabling wafer flow through several dry-etch modules. Shanti continues to support FEOL programs leveraging her expertise in process and tooling development.

• 

  Matthew K Flaugh

  TEL Technology Center

  Matthew Flaugh received a M.S. degree in Physics from West Virginia University in 2016, studying under Dr. Mark Koepke studying temperatures in photoionized plasmas. In 2016, he joined Tokyo Electron as a chemical etch process engineer supporting dry etch development. He currently supports process and tool development on <2nm node development for logic, primarily focused on FEOL applications of dry chemical etch process.

• 

  Toshiki Kanaki

  TEL Technology Center

  Toshiki Kanaki received a PhD in electrical engineering from the University of Tokyo in 2018. In 2018, he joined Tokyo Electron as a process engineer. Since then, he has been working on process development of isotropic gas chemical etching.

• 

  Matthew Lawrence Rednor

  TEL Technology Center

  Matthew Rednor is an etch process engineer supporting development of isotropic etch solutions for advanced logic technology. He received a B.S. degree in Materials Science & Engineering from Carnegie Mellon University with work on equilibrium crystal systems simulation and shape-memory polymer phase transitions. He joined TEL in 2021 focusing on hardware and process development of gas chemical etch and its applications for gate-all-around nanosheet integration.

• 

  Huimei Zhou

  IBM Research

  Huimei Zhou received her Ph.D. degree in Electrical Engineering from University of California, Riverside, CA, USA in 2012, M.S. degree in Physics from Nanjing University, Nanjing, China in 2004. Dr. Zhou worked as Process Integration Engineer in SMIC, shanghai, China; Global Foundries, Singapore and Samsung, Austin, USA, focusing on technology development from 130nm to 28nm. She joined IBM Research in 2015, working on novel devices and reliability from 14nm to 2nm and beyond. In addition to her technical expertise, she has working with diverse teams innovating on the reliability qualification of advanced semiconductor devices and structures. She has 60+ journals/conferences and 70+ patent publications in the area of semiconductor devices, materials and reliability.

• 

  Liqiao Qin

  IBM Research

  Liqiao Qin received a PhD degree in Electrical Engineering from Rensselaer Polytechnic Institute (RPI) in 2011, studying colloidal nanoparticle-based photodetectors. In 2012, she joined GlobalFoundries as an CMP process engineer and supported the W and oxide CMP for different technology nodes. Later she became a device engineer working on developing 14/12nm technology to support high performance low power applications. Liqiao currently works with IBM Research developing gate-all-around nanosheet technology with a focus on device design/ characterization/performance step up and product applications. She has authored or coauthored over 40 papers in scientific journals and conference proceedings.

• 

  Juntao Li

  IBM Research

  Juntao Li received his Ph.D. from College of Nanoscale Science and Engineering of University at Albany – SUNY in 2010. He was a senior engineer of Advanced Materials Characterization at IBM Research at Albany Nanotech. He has worked on advanced analytical characterizations in a variety of emerging semiconductor technologies including 22nm, 14nm, 10nm, 7nm high performance logic, non-volatile memory, gate-all-around nanosheet technology, etc. He is the author or coauthor of more than 100 technical journal papers and conference proceedings, and 1 book chapter. He is a Master Inventor of IBM with over 450 US patents and patent applications.

• 

  Luciana Meli

  IBM Research

  Dr. Luciana Meli is the senior manager for Lithography and Metrology at IBM Semiconductor Technology Research and Development in Albany. In this role, Luciana is responsible for the demonstration and enablement of new lithography tooling, processes, materials, and metrology to support IBM’s leading-edge CMOS device and AI hardware roadmap.
  Luciana received her B.S. in Chemical Engineering from the National University of Mexico, and her PhD from University of Texas at Austin in 2007, where her worked focused on self-assembly of polymer nanocomposites. After post-doctoral work at University of Minnesota and Rensselaer Polytechnic Institute. Dr. Meli is SPIE Senior member and co-author on over 100 publications.

• Nicolas Loubet

  IBM Research

• Peter Biolsi

  TEL Technology Center

• 

  Nelson Felix

  IBM Research

  Nelson Felix joined IBM in 2008 and is currently the Director of Technical Strategy for IBM Semiconductor Research in Albany, NY. Previous to this role, Nelson held multiple management and executive positions in process research, focused on logic patterning, process, and metrology innovations supporting IBM’s leading-edge CMOS device and AI hardware roadmap. Nelson received his B.S. from the University of Massachusetts, Amherst (2002) and his Ph.D. from Cornell University (2007), both in chemical engineering, and his doctoral work centered on the characterization of novel photoresist materials for EUV. Dr. Felix is an SPIE Fellow, and he is co-inventor on over 50 patents and co-author on over 100 publications.

History of the SSDM Paper Award is here

SSDM Best Student Award (BSA)

SSDM Best Student Award is awarded to the best student paper presented at the previous year’s SSDM. This award was established from SSDM 2022.

• 

  Shin-Yi Min

  The University of Tokyo

  Shin-Yi Min received the B.E and M.E degrees in the Department of Electronic Materials Engineering from Kwangwoon University, Seoul, Korea, in 2019 and 2021, respectively. He is currently pursuing the Ph.D. degree in the Department of Electrical Engineering and Information Systems, School of Engineering, The University of Tokyo from 2021 under the supervision of Prof. Shinichi Takagi. He focuses on advanced technology for future CMOS devices such as HfO2-based ferroelectric materials for the gate stack, memory applications, and AI computing. In particular, his main research interests are reservoir computing improvement and clarification by optimizing the operation of HfZrO2 FeFETs.

History of the SSDM Best Student Award is here

SSDM Young Researcher Award (YRA)

SSDM Young Researcher Award is awarded to the first authors of excellent papers presented at the previous year’s SSDM. Authors who are 33 years old or younger as of April 1st of the year following the conference in which the paper was presented are eligible for the award.

• 

  Bert Werner Johan Pollefliet

  KU Leuven

  Bert Pollefliet was born in Bruges, Belgium, in 1999. He received his BSc and MSc degrees in Engineering physics from Ghent University, Belgium, in 2020 and 2022, respectively. During his master thesis, he joined the Conformal Coating of Nanomaterials (CoCooN) lab of Prof. Christophe Detavernier at the Department for Solid State Sciences where he worked on the atomic layer deposition of cobalt for interconnect applications. He is currently pursuing his PhD degree in Materials Engineering at the Materials Engineering Department (MTM) of KU Leuven and the epitaxy team of imec, Belgium, under the supervision of Prof. Clement Merckling. His current research interests include the growth and characterization of silicides contacted to highly doped epitaxial source/drain layers for advanced CMOS applications. In particular, he is currently working on scandium silicide contacts to phosphorous-doped silicon for NMOS devices.

• 

  Gilles Delie

  Imec

  Gilles Delie earned his master’s degree in physics from KU Leuven, Belgium, in 2018. Subsequently, he pursued his PhD in physics at KU Leuven, completing it in 2023. During his doctoral research, he focused on investigating the band alignment of semiconducting two-dimensional transition metal dichalcogenides with underlying oxides, resulting in the publication of several papers. Since 2022, he has joined imec as a researcher within the compute and memory integration department. Here he is part of a team developing the Ru semi-damascene integration approach, which aims to facilitate back-end-of-line pitch scaling down to 18 nm and below. He is currently focussing on airgap incorporation into semi-damascene to further reduce the RC delay.

• 

  Takuya Mitarai

  Photonics Electronics Tech. Res. Assoc., Sumitomo Electric Industries, Ltd.

  Takuya Mitarai received B.E. and M.E. degrees in electrical and electronic engineering from the Tokyo Institute of Technology, Tokyo, Japan, in 2018 and 2020, respectively. In 2020, he joined Transmission Devices Laboratory, Sumitomo Electric Industries, Ltd., Yokohama, Japan. His research interests include mosaic-based ultra-compact Si-photonic devices, and III-V/Si heterogeneous integrated photonic devices.

• 

  Yizhou Chen

  Univ. of Tsukuba

  Yizhou Chen was born in Kunming City, China in 1997. He obtained a Bachelor of Science in Physics from Beijing Normal University, in 2020, and a Master of Engineering in Materials Science from University of Tsukuba, in 2023. At the present he is a second-year student in the doctor’s program in Department of Materials Science, Institute of Pure and Applied Sciences, University of Tsukuba, under the supervision of Professor Kazuhiro Marumoto. His research interests focus on the development of functional semiconductor materials and their devices, especially on organic-inorganic hybrid perovskite materials. Currently, he is working on the elucidation of the charge states of buried interfaces inside Sn-based perovskite solar cells, using operando electron spin resonance (ESR) method.

• 

  Wenzhong Zhang

  Tohoku University, Matsumoto Lab.

  I studied for my undergraduate and master's degrees in China. My undergraduate degree was at Nanjing University of Science and Technology and my master's degree was on Dalian University of Technology, where my research direction was on the synthesis of organic solar cells. I have done a lot of synthesis experiments on n-type materials for batteries, and have a good grasp of organic synthesis. I studied in the Matsumoto Laboratory of Tohoku University for my doctoral degree. The research content during my doctoral period was more macroscopic than that during my master's period, that is, using vacuum evaporation technique to fabricate ionic liquid crystal (ILC) films and electronic devices based on ILC films. In the future, I hope to find a postdoctoral position after graduating with a Ph.D. and combine my molecular synthesis and device fabrication capabilities in my future life to continue to engage in related research work.

• 

  Samarth Jain

  National University of Singapore

  Samarth Jain is the founder of a neuromorphic AI chip company called BMLABS https://bmsemi.org/ with branches in Singapore and India. He holds a master's degree from the Hong Kong University of Science and Technology. Samarth has an extensive background in advanced semiconductor technologies, having worked at Micron on 3D NAND, and subsequently at the National University of Singapore (NUS) on developing 3D NAND etching, 2D materials, and RRAMs. He is now fully dedicated to leading his company, focusing on pioneering innovations in AI hardware.

• 

  Farah Basaric

  Forschungszentrum Jülich GmbH

  Farah Basaric is a PhD student at Forschungszentrum Jülich GmbH, specializing in quantum transport in nanostructures. Current efforts on nanowire-based hybrid devices represent the continuation of her work throughout her Master thesis at RWTH Aachen University, where the objective was to further understanding of core/shell GaAs/InAs nanowires in terms of the interplay between their crystal structure and transport properties. Combined with an in-situ deposited Al layer, such structure forms a device known as Josephson junction, and represents a promising platform on the road towards the realization of Andreev level qubits and topological computation. A state-of-the-art selective area, self-catalyzed growth approach to single crystal phase GaAs/InAs nanowires and low-temperature characterization throughout her work, resulted in observance of the keynote quantum interference effects, thus providing a good building block in further efforts towards the optimization of nanowire-based Josephson junction. Dedicated to deepening understanding within her specialization, she frequently partakes as a speaker at conferences and workshops. Farah enjoys reading classical literature, playing the piano, analog photography, painting and hiking in her spare time.

• 

  Linyu Huang

  Kyushu University

  Huang Linyu received her master’s degree in engineering from Kyushu University under the supervision of associate professor Keisuke Yamamoto in 2024. She will go on to a Ph.D. program in the same lab. Her research was inversion mode n-channel thin-film-transistor fabrication on polycrystalline Ge on a glass substrate at low temperature. Now, she is working on CMOS fabrication process design on poly-Ge and optimizing the n-channel TFT on a flexible substrate at low process temperature. She will also focus on the defect characterization of poly-Ge and dopant activation method after ion implantation on polycrystalline Ge or other group 4 semiconductor alloy materials.

• 

  Takamitsu Ishiyama

  University of Tsukuba

  Takamitsu Ishiyama was born in Tokyo, Japan, in 1998. He received the M. E. degree in semiconductor engineering from the University of Tsukuba under the supervision of Associate Professor Kaoru Toko in 2023. Currently, he is a second-year student in the D. E. program, focusing on thin-film semiconductor engineering and materials informatics. He proposes new methods for rapidly analyzing microscopic images with deep learning and improving semiconductor properties using Bayesian optimization. After completing his doctoral program, he plans to pursue an academic career to further his research and contribute to advancements in semiconductor technology.

History of the SSDM Young Researcher Award is here

Call for 2024 SSDM Award Nomination

The SSDM Award was established to recognize outstanding contributions to academic or industrial development in the field of solid state devices and materials.
Papers to be nominated for the 2024 SSDM Award should be among those that have been presented between the 1st SSDM conference in 1969 and the 50th SSDM conference in 2018.

The SSDM Award will ultimately be decided by the SSDM Organizing Committee after a recommendation is made by the SSDM Award Nomination Committee.

The recommendation will be in accordance with the following two criteria.

• 1) Originality

  The award-winning selection must be original, and must have had significant theoretical or practical impact in the field of solid state devices and materials.

• 2) Contribution

  The author(s) of the award-winning selection must have played or be playing a pioneering or leading role, with globally outstanding contributions in the technological field.

Candidate and Nominator Eligibility

• – Candidates Eligible for the Award

  All authors who presented papers between the 1st SSD conference in 1969 and the 50th SSDM conference in 2018, excluding papers written by this year’s Organizing Committee Chair and Award Nomination Committee Chair.

• – Persons Eligible for Nominating Candidates

  Anyone, excluding this year’s members of the SSDM Award Nomination Committee

Submission Process for SSDM Award Nominations

The following is the process for submitting nominations.

• – Before deciding on a candidate for the award, confirm the eligibility of nominators and candidates once again.
• – Download the Nomination Form.
  [ SSDM Award Nomination Form (MS‐Word) ]
• – Fill out the Nomination Form and send it to the SSDM Secretariat by the deadline.
  Nomination deadline: May 13, 2024 CLOSED

History of the SSDM Award is here