History of SSDM Young Researcher Award

Year of Award Year of presentation Presentation number Paper Title Awarded Author Affiliation (Country)
2022 D-2-04 Tumor-on-a chip in 3D microfluidic device for immunotherapy study Yu-Chen Chen National Tsing Hua University (Taiwan)
F-7-04 A High-Efficiency, Reliable Multilevel Hardware-Accelerated Annealer with In-Memory Spin Coupling and Complementary Read Algorithm Yun-Yuan Wang Macronix International Co., Ltd (Taiwan)
C-1-01 Group IV Semiconductor Alloy Thin Films for Environmentally Friendly Shintaro Maeda University of Tsukuba (Japan)
F-10-02 Neural Network Hardware Accelerator using Memristive Crossbar Array based on Wafer-Scale 2D HfSe2 Sifan Li National University of Singapore (Singapore)
K-8-01 Electro-optic imaging system using a CMOS image sensor with a dual-layer on-pixel polarizer Ryoma Okada Nara Institute of Science and Technology (Japan)
B-3-02 Vertical Alignment Control of Self-Ordered Multilayered Ge Nanodots on SiGe Wei-Chen Wen IHP - Leibniz Institute for High Performance Microelectronics (Germany)
A-10-03 Polarization-Independent Enhancement of Optical Absorption in a GaAs Quantum Well Embedded in an Air-bridge Bull's-eye Cavity Sangmin Ji The University of Tokyo (Japan)
E-3-06 Utilizing Dual-stacked IGZO channel structure to Achieve Optical Memories Application Kuan-Ju Zhou National Sun Yat-Sen University (Taiwan)
C-10-06 Highly Efficient Spin Current Source Using BiSb Topological Insulator / NiO Bilayers Julian Sasaki Tokyo Institute of Technology (Japan)
2021 A-8-01 Computing-in-Memory Demonstration of Multiple-State (>8) Analog Memory Cell with Ultra-Low (<1 nA/cell) Current Enabled by Monolithic CAAC-IGZO FET + Si CMOS FET Stack for Highly-Efficient AI Applications Satoru Ohshita Semiconductor Energy Lab. Co., Ltd. (Japan)
L-1-03 A Novel 1T2R Self-Reference Physically Unclonable Function Suitable for Advanced Logic Nodes for High Security Level Applications Yu-Hsuan Lin Macronix Int'l Co., Ltd. (Taiwan)
D-1-05 “Regrowth-free” Fabrication of AlGaN/GaN HBT with N-p-n Configuration Takeru Kumabe Nagoya Univ. (Japan)
E-5-04 Lasing from a valley photonic crystal ring resonator with a bearded interface Ryosuke Miyazaki Univ. of Tokyo (Japan)
F-2-02 Charge/Discharge Reactions via LiPON/Multilayer-Graphene Interfaces without Li+ Desolvation/Solvation Processes Satoshi Yamamoto Nagoya Univ. (Japan)
H-6-06 Universal Method on Charge Carrier Mobility and Series Resistance Extraction in Two-Dimensional Field-Effect Transistors Yu-Chieh Chien National Univ. of Singapore (Singapore)
I-5-03 Room-temperature Spin Injection and Spin-to-charge Conversion in a Ferromagnetic Semiconductor / Topological Insulator Heterostructure Shobhit Goel Univ. of Tokyo (Japan)
J-2-03 High mobility hydrogenated indium oxide thin-film transistors (InOx:H TFTs) formed by low-temperature solid phase crystallization Taiki Kataoka Kochi Univ. of Tech. (Japan)
K-6-04 First Demonstration of Photoresponsivity in a Polycrystalline Ge-based Thin Film Takuto Mizoguchi Univ. of Tsukuba (Japan)
2020 A-6-05 Millisecond Post Deposition Annealing for Improving the EOT and Dit in TiN/HfO2/SiO2/Si Gate Stacks using Flash Lamp Annealing Hikaru Kawarazaki SCREEN Semiconductor Solutions Co., Ltd.
B-2-01 Impact of Zr Concentration on Time-Dependent Dielectric Breakdown of HfZrO-based Ferroelectric Tunnel Junction (FTJ) Memory Marina Yamaguchi KIOXIA Corporation
D-7-01 Large Signal Results at 6 GHz and record ft/fmax for AlN/GaN/AlN HEMTs Austin Lee Hickman Cornell University
E-1-04 Backside Integration of III-V/Si Hybrid Laser in a Si-SiN Photonics Platform Quentin Wilmart Univ. Grenoble Alpes, CEA, LETI
F-2-01 Thin-Film Thermoelectric Generators with Si1-xGex Formed by Layer Exchange Mikie Tsuji University of Tsukuba
H-9-04 Understanding the tunneling behavior in 2D based floating gate type memory device by measuring floating gate voltage Taro Sasaki The University of Tokyo
I-1-02 Anisotropic spin-orbit torques in epitaxial ruthenium oxide Shutaro Karube Tohoku university
L-9-04 A Dual-mode SAR ADC Enabling On-chip Detection of Off-chip Power Noise Measurements by Attackers Takuya Wadatsumi Kobe University
2019 N-2-04 3D-stacked Highly Strained SiGe/Ge Gate-All-Around (GAA) pFETs Fabricated by 3D Ge Condensation Junkyo Suh Stanford University
K-5-03 (111) Vertical-type 2DHG Diamond MOSFETs with Hexagonal Trench Structures Jun Tsunoda Waseda University
A-4-02 Development of Wireless Opto-Neural Probe with Upconversion Nanoparticles (UCNP) for Optogenetics Shota Urayama Tohoku University
D-6-01 Demonstration of Electromechanical Device Based on 2D Piezoelectric Materials for Nanogenerator Applications Naoki Higashitarumizu The University of Tokyo
G-4-01 Development of High Yield Layer Transfer Process of Single Crystalline Silicon Thin Film on Plastic Substrate and Its Application to Floating Gate Memory Fabrication Tomotaka Hirano Hiroshima University
M-1-03 An Information Leakage Sensor Based on Measurement of Laser-Induced Opto-Electric Bulk Current Density Kohei Matsuda Kobe University (– 2020.03)
Sony Semiconductor Solutions Corporation (2020.04 –)
2018 C-4-04 Impact of channel thickness fluctuation on performance of bilayer tunneling field effect transistors K. Kato Univ. of Tokyo (Japan)
C-6-04 Investigation of Switching Characteristics for Silicon Doped Hafnium Oxide FeFET T. Ali Fraunhofer IPMS Center Nanoelectronic Technologies (Germany)
D-4-02 Demonstration of β-(AlGa)2O3 (010) metal-semiconductor field-effect transistors with high breakdown voltage over 900 V H. Okumura Univ. of Tsukuba (Japan)
K-3-03 A rapid protein 2D-fingerprinting device using gel-free separation materials and label-free UV detection for proteomics T. Sakamoto Panasonic Corp. (Japan)
M-2-04 Direct Electroluminescence Imaging of Transition Metal Dichalcogenides J. Pu Nagoya Univ. (Japan)
A-5-04 New Operation Mode of VO2-Channel Mott Transistors for Ultra-Sharp ON/OFF Switching T. Yajima Univ. of Tokyo (Japan)
J-4-04 1TFT-1RRAM Cell on Polymeric Substrate as Non-Volatile Memory Element Enabling Future Flexible Electronic Platforms A. Lebanov imec (Belgium), KU Leuven (Belgium)
J-6-05 A 125Mfps Global Shutter CMOS Image Sensor with Burst Correlated Double Sampling during Photo-Electrons Collection M. Suzuki Tohoku Univ. (Japan)
2017 K-3-01 A new kinetic model for thermal oxidation of Ge X. Wang Univ. of Tokyo, Japan
D-1-02 Differential Contact RRAM Pair for Advanced CMOS Logic NVM applications W. -T. Hsieh National Tsing Hua Univ., Hsinchu, Taiwan
F-2-04 Development of Vertically-Stacked Multi-Shank Si Neural Probe Array with Sharpened Tip for Cubic Spatial Recording T. Harashima Tohoku Univ., Japan
A-2-06 Current Density Dependence of Asymmetric Magnetoresistance in Pt/Py Bilayers under Various Magnetic Field Strength T. Li Kyoto Univ., Japan
J-4-05LN Chemical Sensing using Graphene-based Surface-Acoustic-Wave Sensor S. Okuda Osaka Univ., Japan, Mitsubishi Electric Corp., Japan
2016 B-3-05 Multi-level Operation of a High-speed, Low Power Topological Switching Random-access Memory (TRAM) Based on a Ge Deficient GexTe/Sb2Te3 Superlattice H.Shirakawa Nagoya Univ., Japan
B-7-05 Exploitation of RRAM Variability to Improve On-line Unsupervised Learning in Small-scale Spiking Neural Networks T.Werner CEA-LETI, France
H-2-02 Development of Molecularly Imprinted Polymer-Gate Field Effect Transistor for Sugar Chain Sensing S.Nishitani Univ. of Tokyo, Japan
G-4-02 Experimental Demonstration of a Josephson Junction under Spin Current Injection M.Ishitaki Kyushu Univ., Japan
2015 N-2-2 Ω-Gate Nanowire Transistors Realized by Sidewall Image Transfer Patterning: 35nm Channel Pitch and Opportunities for Stacked-Nanowires Architectures L. Gaben CEA-LETI, STMicroelectronics, IMEP-LAHC, France
O-4-4 Area-Efficient Non-volatile Carry Chain Based on Pass-Transistor/Atom-Switch Hybrid Logic X. Bai NEC Corp., Japan
G-5-3 Thermally-Stable High Sn Concentration (~9%) GeSn on Insulator by Ultra-Low Temperature (~180°C) Solid-Phase Crystallization Triggered by Laser-Anneal Seeding R. Matsumura Kyushu Univ., JSPS Research Fellow, Japan
F-7-3 In situ Monitoring of Extracellular Matrix Based on Chondrocytes Behavior using Biologically-coupled Field Effect Transistor H. Satake Univ. of Tokyo, Japan
P-3-5 Millimeter-Wave Detector Using Magnetic Tunnel Junctions With Perpendicularly Magnetized L10-Ordered FePd Free Layer K. Mukaiyama Tohoku Univ. Japan
D-3-6L Direct Evidence of Defect-defect Correlation in Atomically Thin MoS2 Layer by Random Telegraphic Signals Observed in Back-gated FETs N. Fang Univ. of Tokyo, Japan
2014 J-2-2 Improvement of S-factor method for evaluation of MOS interface state density W.-L. Cai Univ. of Tokyo, Japan
K-1-6 Heat protection circuit with polymer PTC for flexible electronics T. Yokota Univ. of Tokyo, Japan
D-1-6 Ultra-High Selective Gas Sensors: novel approaches and future developments M.W.G Hoffmann Braunshweig Univ. of Technology
M-1-4 Excitation of Electric-Field-induced Spin Wave in the Strained Garnet Ferrite Thin Films Using Sub-Picosecond Pulsed Wave M. Adachi Univ. of Tokyo, Japan
E-4-4L 3.3 kV/1500 A Power Modules for the World's First All-SiC Traction Inverter K. Hamada Mitsubishi Electric Corp., Japan
2013 D-3-2 Channel Length Scaling Limits of III-V Channel MOSFETs Governed by Source-Drain Direct Tunneling S. Koba Kobe Univ., Japan
A-2-4 Excellent Scalability Including Self-Heating Phenomena of Vertical-Channel Field-Effect-Diode (FED) Type Capacitorless One Transistor DRAM Cell T. Imamoto Tohoku Univ., Japan
K-1-3 High Speed Waveguide Integrated Lateral P-I-N Ge on Si Photodiode with very Low Dark Current L. Virot Institut d'Electronique Fondamentale, CEA-Leti and STMicroelectronics, France
G-1-5 An implantable CMOS device for functional brain imaging under freely moving experiments of rats M. Haruta Nara Inst. of Sci. and Tech., Japan
F-1-5 Gate Control of Spatial Electron Spin Distribution in Persistent Spin Helix State Y. Kunihashi NTT BRL, Japan
C-3-3 Transport Properties and Defects at the Intersection of CVD Graphene Domains Y. Ogawa Kyushu Univ., Japan
2012 D-6-4 Nickel Stanogermanide Ohmic Contact on N-type Germanium-Tin (Ge1-xSnx) using Se and S Implant and Segregation Y. Tong National Univ. of Singapore, Singapore
G-2-3 Integration of 1-bit CMOS Address Decoders and Single-Electron Transistors Operating at Room Temperature R. Suzuki Univ. of Tokyo, Japan
I-9-3 Shape-memory polymer microvalves and its application to a field-programmable valve array H. Takehara Univ. of Tokyo, Japan
C-5-5L Graphene ReRAM towards All Graphene LSIs: Experimental Demonstration of Two-terminal ReRAM Operation in Electrically Broken Mono- and Multi-layer Graphene A. Shindome Tokyo Tech and Keio Univ., Japan
2011 E-3-3 On the Si Surface Flattening Effect and Gate Insulator Breakdown Characteristic of Radical Reaction Based Insulator Formation Technology R. Kuroda Tohoku Univ., Japan
C-3-1 Improvement of thermal stability in High Density Ta2O5 3D capacitor by additional thin SiO2 layer M. Detalle IMEC, Belgium
D-8-4 Enhanced Degradation by NBT stress in Si Nanowire Transistor K. Ota Toshiba Corp., Japan
H-4-4 Brain interface device with permeable hydrogel membrane for in vivo analysis of neural cells H. Takehara Univ. of Tokyo, Japan
2010 B-2-2 Single-Crystalline (100) Ge Stripes with High Mobilities Formed on Insulating Substrates by Rapid-Melting-Growth with Artificial Single-Crystal Si Seeds K. Toko Kyushu Univ., Japan
E-3-5 Dynamics of the Charge Centroid in MONOS Memory Cells during Avalanche Injection and FN Injection Based on Incremental-Step-Pulse-Programming J. Fujiki Toshiba Corp., Japan
I-5-3 The Unique Phenomenon in the Amorphous In2O3-Ga2O3-ZnO TFTs Degradation under the Dynamic Stress M. Fujii NAIST, Japan
D-4-3 Demonstration of a Silicon photonic Crystal Slab LED with Efficient Electroluminescence S. Nakayama Univ. of Tokyo, Japan
2009 B-7-1 High Electron Mobility Ge n-Channel MOSFETs with GeO2 grown by High Pressure Oxidation C. H. Lee Univ. of Tokyo, Japan
D-4-2 Effect of Via-Profile on the Via Reliability in Scaled-down Low-k/Cu Interconnects I. Kume NEC Electronics Corp., Japan
G-7-2 Physical model for reset state of Ta2O5/TiO2 stacked ReRAM Y. Sakotsubo NEC Corp., Japan
I-1-7 Demonstration of Quality Factor over 10,000 in Three-Dimensional Photonic Crystal Nanocavity by Cavity Size Control A. Tandaechanurat Univ. of Tokyo, Japan
I-4-2 Fabrication of InAs Nanowire Vertical Surrounding-Gate Field Effect Transistor on Si Substrates T. Tanaka Hokkaido Univ., Japan
2008 C-7-1 Low-Loss Magnetic Films of Ni-Zn Ferrite by Low-Temperature PVD Method for RF-CMOS Application K. Kaneko NEC Electronics Corp., Japan
J-9-2 Resistive Switching Ion-Plug Memory for 32-nm Technology Node and Beyond K. Ono Hitachi Ltd., Japan
I-9-4 Direct Observation of Field-Induced Carrier Dynamics in Pentacene Thin-film Transistors by ESR Spectroscopy H. Matsui AIST and Univ. of Tokyo, Japan
E-6-2 Development of a CMOS image sensor for in situ brain functional imaging in freely-moving mouse A. Tagawa NAIST
C-3-3 Huge Magnetoresistance Effect in Semiconductor based Nanostructures with Zinc-blende MnAs Nanoparticles P. N. Hai Univ. of Tokyo, Japan
2007 J-8-2 Two-Dimensional Electron Gas Switching in an Ultra Thin Epitaxial ZnO Layer on a Ferroelectric Gate Structure Y. Kaneko Matsushita Electric Industrial Co., Ltd., Japan
D-3-1 A 0.49-6.50 GHz Wideband LC-VCO with High-IRR in a 180 nm CMOS Technology Y. Kobayashi Tokyo Tech., Japan
H-8-1 Hall effect measurements of polycrystalline pentacene TFTs with double gate structures Y. Takamatsu Univ. of Tokyo, Japan
D-7-4 Rapid and High Sensitive Detection of Bacteria Sensor using a Porous Ion Exchange Film K. Miyano Osaka Univ., Japan
J-9-5 Single charge sensitivity of single-walled carbon nanotube single-hole transistor T. Kamimura Osaka Univ.and CREST-JST, Japan
2006 J-7-4 The Highly Reliable Evaluation of Mobility in an Ultra Thin High-k Gate Stack with an Advanced Pulse Measurement Method R. Iijima Toshiba Corp., Japna
E-10-3 High Critical Electric Field Exceeding 8 MV/cm Measured Using AlGaN p-i-n Vertical Conducting Diode on n-SiC Substrate A. Nishikawa NTT Basic Research Labs., NTT Corp., Japan
F-2-2 A Highly Reliable MIM Technology with non-Crystallized HfOx Dielectrics Using Novel MOCVD Stacked TiN Bottom Electrodes T. Ohtsuka Panasonic Semiconductor Engineering Co., Ltd., Japan
D-7-4 Analysis of hole trapping into pentacene FET by Optical Second Harmonic Generation and C-V measurements E. Lim Tokyo Tech, Japan
H-8-1 Strained SiGe-On-Insulator N-MOSFET with Silicon Source/Drain for Drive Current Enhancement G. H. Wang National Univ. of Singapore, Singapore
2005 A-3-2 Permittivity Enhancement of Hf(1-x) Six O2 Film with High Temperature Annealing K. Tomida Univ. of Tokyo, Japan
F-10-3 A pixel circuit for AMOLED consisting of OTFTs and OLED K. B. Choe Dong-A Univ., Korea
G-2-8 Fowler-Nordheim current oscillations in Si(111)/SiO2/twisted-Si(111) tunneling structures D. Moraru Shizuoka University, Japan
I-5-2 Normally-off Operation of Non-polar AlGaN/GaN Heterojunction FETs Grown on R-plane Sapphire M. Kuroda Matsushita Electric Industrial Co., Ltd., Japan
2004 A-5-1 Successful CMOS Operation of Dopant-Segregation Schottky Barrier Transistors (DS-SBTs) A. Kinoshita Toshiba Corp., Japan
B-10-3 Planar Double Gate CMOS transistors with 40nm metal gate for multipurpose applications M. Vinet CEA/DRT-LETI, France
H-2-3 Room-Temperature Demonstration of Low-Voltage Static Memory Based on Negative Differential Conductance in Silicon Single-Hole Transistors M. Saitoh Univ. of Tokyo, Japan
F-10-3 Bending and recovery tests of organic field-effect transistors T. Sekitani Univ. of Tokyo, Japan
2003 A-2-4 Comparison of the Interconnect Capacitances for Various SRAM Cell Layouts to Achieve High Speed, Low Power SRAM Cells Y. Tsukamoto Renesas Technology Corp., Japan
D-1-5 Measurement of Extension Structures in Deep Sub-Micron MOSFETs by Scanning Capacitance Microscopy based on Frequency Modulation Control Y. Naitou NEC Corp., Japan
E-3-3 Electronic Charged States of Single Si Quantum Dots with Ge Core as Detected by AFM/Kelvin Probe Technique Y. Darma Hiroshima Univ., Japan
F-7-2 Coupled Waveguide Devices Based on Autocloned Photonic Crystals M. Shirane NEC Corp., Japan
G-4-2 Micro Cu Bump Interconnection on 3D Chip Stacking Technology K. Tanida ASET, Japan