History of SSDM Award

Year of the award Awarded thesis
Conference number held Year of presentaion Thesis number Name of awardees Title of thesis
14th 1982 A-2-LNI Eiichi Suzuki,Yutaka Hayashi, Kenichi Ishii,
Hisato Hiraishi
Electrotechnical Laboratory, Japan
A Low-Voltage Alterable Metal-Oxide-Nitride-Oxide-Semiconductor Memory with Nano-Meter Thick Gate Insulators (NM-MONOS)
16th 1984 B-6-2 Akio Nakagawa, Hiromichi Ohashi,and Tsuneo Tsukakoshi
Toshiba Research and Development Center, Japan
High Voltage Bipolar‐Mode MOSFET with High Current Capability
19th 1987 C-3-1 Kazuyuki Tsunokuni1, Kazuo Nojiri1, Sumi Kuboshima2, and Kado Hirobe3
1 Musashi Works, Hitachi, Ltd., 2 Hitachi Microcomputer Engineering, Ltd., 3 Kanagawa Works, Hitachi, Ltd.
The Effect of Charge Build-up on Gate Oxide Breakdown during Dry Etching
33rd 2001 D-8-3 T. Hasegawa1,2, K. Terabe1,2, T. Nakayama1,2, and M. Aono1,2,3
1 Surface and Interface Laboratory, RIKEN (The Institute of Physical and Chemical Research), 2 CREST, Japan Science & Technology Corporarion (JST), 3 Department of Precision Science and Technology, Osaka University
Quantum Point Contact Switch using Solid Electrochemical Reaction
7th 1975 A-5-2 I. Yoshida, M. Kubo and S. Ochi
Central Research Laboratory, Hitachi, Ltd.
A High Power MOSFET with a Vertical Drain Electrode and Meshed Gate Structure
26th 1994 S-IV-3 T. Shibata, H. Kosaka, H. Ishii, and T. Ohmi
Tohoku University
A Neuron-MOS Neural Network Using Low-Power Self-Learning-Compatible Synapse Cells
25th 1993 D-9-4 T. Enoki, Y. Umeda and Y. Ishii
NTT LSI Laboratories
0.05-µm-Gate InAlAs/InGaAs HEMT and Reduction of Its Short-Channel Effects
11th 1979 B-3-4 S. Arai, Y. Itaya, Y. Suematsu and K. Kishino
Tokyo Institute of Technology
1.5-1.6 µm Wavelength (100) GaInAsP/InP DH Lasers
19th 1987 C-3-6 H. Shinriki, Y. Nishioka and K. Mukai
Central Research Laboratory Hitachi Ltd.
Highly Reliable Ta2O5/SiO2 Double Dielectric Films on Poly Crystalline Silicon
24th 1992 S-IV-3 A.Toriumi, T. Mizuno, M. Iwase, M. Takahashi, H. Niiyama, M. Fukumoto, S. Inaba, I. Mori, and M. Yoshimi
ULSI Research Center, Toshiba Corporation
High Speed 0.1µm CMOS Devices Operating at Room Temperature
9th 1977 C-1-1 H. Suzuki, K. Suyama, K. Odani, and M. Fukuta
Fujitsu Laboratories Ltd.
C-band 10W Power GaAs MESFET with an Internal Matching Circuit

9th 1977 C-1-2 Y. Aono, A. Higashisaka, T. Ogawa and F. Hasegawa
Central Research Laboratories, Nippon Electric Co. Ltd.
X- and Ku-band Performance of Submicron Gate GaAs Power FETs
13th 1981 A-3-8 I. Kato, T. Ito, S. Inoue, T. Nakamura, and H. Ishikawa
Fujitsu Laboratories Ltd.
Ammonia annealed SiO2 films for thin gate insulator
17th 1985 C-3-9
T. Sekigawa, Y. Hayashi1, K. Ishii2, and S. Fujita3
Nanoelectronics Research Institute of AIST, 1 Nanosystem Research Institute of AIST, 2 (Ex) Nanoelectronics Research Institute of AIST, 3 Corporate Technology Planning Center, Ricoh Company, Ltd.
XMOS Transistor for a 3D-IC
18th 1986 A-7-4 K. Yamada
Univ. of Tsukuba
Thermodynamical Approach to a New High Dielectric Capacitor Structure: W/HfO2/W
25th 1993 PB-3-9 K. Natori
Univ. of Tsukuba
Ⅰ-Ⅴ Characteristics of SOI MOSFETs in Ballistic Mode
2nd 1970 1-1 S. Furukawa and H. Ishiwara
Tokyo Tech.
Vacancy Distribution Theory for Ion-Implanted Target
3rd 1971 5-2 H. Sakaki and T. Sugano
Univ. of Tokyo
Anistropic Channel Conductivity of a MOS Transistor on the (110) Surface of Silicon
14th 1982 B-2-3 H. Soda, Y. Motegi, and K. Iga
Tokyo Tech.
Threshold Condition and Design of Surface Emitting GaInAsP/InP Injection Lasers
19th 1987 C-4-2 H. Matsunami, N. Kuroda, W. S. Yoo, S. Nishino, and K. Shibahara
Kyoto Univ., Japan
Step-Controlled VPE Growth of SiC Single Crystals at Low Temperatures
22th 1990 S-CII-4 Y. Hayashide, H. Miyatake, J. Mitsuhashi, M. Hirayama, T. Higaki, and H. Abe
Mitsubishi Electric, Japan
Fabrication of Storage Capacitance-Enhanced Capacitors with a Rough Electrode

22th 1990 S-CII-5 H. Watanabe, N. Aoto, S. Adachi, T. Ishijima, E. Ikawa, and K. Terada
NEC, Japan
A New Stacked Capacitor Structure using Hemispherical-Grain(HSG) Poly-Silicon Electrodes
24th 1992 S-1-1 I. Akasaki and H. Amano
Meijo Univ., Japan
Room Temperature Ultraviolet/Blue Light Emitting Devices Based on AlGaN/GaN Multi-Layered Structure
3th 1971 5-5 H. Hara, T. Sato, Y. Takeishi, K. Ohuchi, H. Tango, Y. Ohmori, H. Iizuka, Y. Yasuda, and F. Masuoka
Toshiba Research and Development Center, Japan
Avalanche-Injection MOS Read-Only Memory
6th 1974 B-3-3 M. Esashi and T. Matsuo
Tohoku Univ., Japan
Biomedical Cation Sensor Using Field Effect of Semiconductor
4th 1972 6-1 T. Warabisako, I. Yoshida, and T. Tokuyama
Hitachi, Japan
Properties of MOS Structures Prepared on Substrates Having Ion-Implanted Impurity Distribution Profile
12th 1980 C-3-9
T. Mimura, S. Hiyamizu, H. Hashimoto, and H. Ishikawa
Fujitsu Labs., Japan
An Enhancement-Mode High Electron Mobility Transistor for VLSI
6th 1974 B-2-1 H. Abe
Mitsubishi, Japan
The Application of Gas Plasma to the Fabrication of MOS LSI (Invited)

18th 1986 B-8-4 Y. Matsushita, M. Wakatsuki, and Y. Saito
Toshiba, Japan
Improvement of Silicon Surface Quality by H2 Anneal
12th 1980 A-4-7 T. Sakai, Y. Kobayashi, H. Yamauchi, M. Sato, and T. Makino
NTT, Japan
High Speed Bipolar ICs Using Super Self-Aligned Process Technology
11th 1979 A-3-7 K. Izumi, M. Dohken, and H. Ariyoshi
NTT, Japan
High Speed C-MOS IC Using Buried SiO2 Layers Formed by Ion Implantation
5th 1973 3-4 H. Yonezu, I. Sakuma, T. Kamejima, M. Ueno, K. Kobayashi, K. Nishida, Y. Nannichi, and I. Hayashi
Nippon Electric, Japan
Degradation of AlxGa1-xAs Double Heterostructure Lasers
10th 1978 A-1-4 M. Koyanagi and N. Hashimoto
Hitachi, Japan
Novel High Density, Stacked Capacitor MOS RAM
7th 1975 A-1-1 Y. Horiike and M. Shibagaki
Toshiba, Japan
A New Chemical Dry Etching
11th 1979 C-3-4 M. Tajima, A. Yusa*, and T. Abe**
ETL, *Komatsu Electronic Metals and **Shin-Etsu Handotai, Japan
Characterization of Residual Impurities in Highly Pure Si Crystals by Photoluminescence Technique
6th 1974 A-1-1 T. Tsukada
Hitachi, Japan
Buried-Heterostructure Injection Lasers
1st 1969 4-1 Y. Tarui, Y. Hayashi, and T. Sekigawa
ETL, Japan
Diffusion Self-Aligned MOST: A New Approach for High Speed Device