INVITED SPEAKERS

CORE AREAS

Area 1

Advanced Gate Stack / Si Processing Science

“Challenges for PMOS metal gate electrodes and solutions for low power applications”
J. Schaeffer, Freescale Semiconductor Inc., USA

“A Study for PMOS metal gate electrodes and solutions for low power applications”
S. Zafar, IBM, USA

“Study of Dopant Diffusion and Defect Evolution for Advanced Ultra Shallow Junctions based on an Atomistic Modeling”
T. Noda, Matsushita Electric Industrial Co., Ltd., Japan

“Schottky Barrier and Stability of Metal/High-k Interfaces: Theoretical View”
T. Nakayama, Chiba Univ., Japan

Area 2

“Wiring technology for analog and mixed signal LSIs” A. Matsuzawa, Tokyo Tech., Japan

“Si-Based Infrared Light Emitters Using Semiconducting Iron Disilicide”
T. Suemasu, Univ. of Tsukuba, Japan
S. Murase, Univ. of Tsukuba, Japan
Y. Ugajin, Univ. of Tsukuba, Japan
M. Suzuno, Univ. of Tsukuba, Japan

“Low-k/Cu Integration Consistent from 90nm thru 32nm”
T. Nogami, IBM, USA

“Stress Migration Phenomenon in Narrow Copper Interconnects”
T. Nakamura, Fujitsu Labs. Ltd., Japan
T. Suzuki, Fujitsu Labs. Ltd., Japan

“Generation Mechanism of Etching Damages on Low-k SiOCH Films and Development of Novel Damage Evaluation Technique”
M. Hori, Nagoya Univ., Japan

Area 3

CMOS Devices /Device Physics

“RTN Effects in Scaled Flash Memory Arrays”
A. S. Spinelli, Politecnico di Milano, Italy

“Technology Oriented Analytical Models of MOSFETs in the Quasi Ballistic Regime” R. Clerc, IMEP, France

“Low Standby Power CMOS Process Integration Scheme for 45-32 nm node”
K. Imai, NEC Electronics, Japan

Area 4

Advanced Memory Technology

“Overview and Future Challenges of Floating Body RAM Technologies”
T. Shino, Toshiba Corp., Japan

“3D Device Stacking Technology for Future Memory”
S. M. Jung, Samsung Electronics Co., Ltd., Korea

“Current Status and Future View of Phase Change Memory”
Y. Matsui, Hitachi Ltd., Japan

“Current Development Status and Future Challenge of Metal Oxide RRAM Technologies”
N. Awaya, Sharp Corp., Japan

Area 5

Advanced Circuits and Systems

“Next generation compact model for digital and analog circuit design”
T. Ohguro, Toshiba Corp., Japan

“Characterization and Modeling of Layout Dependent Parametric Vairability of Nanometer Devices”
C. Guardiani, PDF Solutions, Italy

“RF CMOS Circuits - Overview and Perspective -”
T. Tsukahara, Univ. of Aizu, Japan

“Compensation techniques for integrated analog device issues”
A. Matsuzawa, Tokyo Tech., Japan

Area 6

Compound Semiconductor Circuits, Electron Devices and Device Physics

“Next Generation High-Efficiency RF Transmitter Technology for Basestations”
P. M. Asbeck, Univ. of California, San Diego

“Parasitic effects and reliability issues on GaN based HEMTs”
G. Meneghesso, Univ. of Padova, Italy

“Class-F Microwave Amplifier Design Using GaAs-HBT and GaN HEMT”
K. Honjo, Univ. of Electro-Communications, Japan

“Growth of InAs Channel HEMT Structure on Si substrate and it's Possible Application on Low Power Logic”
E. Y. Chang, National Chiao Tung Univ., Taiwan

Area 7

Photonic Devices and Device Physics

“High-Speed Quantum Dot Lasers”
P. Bhattacharya, Univ. of Michigan, USA

“MOCVD Growth of Quantum-Dot Optical Devices”
K. Kawaguchi, Fujitsu Labs. Ltd., Japan

“Nanophotonic technologies for PC-SMZ-based all-optical flip-flop switch: PC-FF”
Y. Sugimoto, Univ. of Tsukuba, Japan
K. Asakawa, Univ. of Tsukuba, Japan

“Quantum Confined Ultra-Thin Silicon Light-Emitting Transistor for On-Chip Optical Interconnection”
S. Saito, Hitachi Ltd., Japan

Special Session

“LSI on-chip optical interconnect ion with Si nano-photonics”
J. Fujikata, MIRAI-Selete, Japan

“Plasmonic Crystals and Nanophotonic Sensing Devices”
T. A. Kelf, Hokkaido Univ., Japan

“GaN-based High-speed Intersubband Optical Switches”
N. Iizuka, Toshiba Corp., Japan
N. Suzuki, Toshiba Corp., Japan

“Widely Tunable Integrated DBR Laser Array with Fast Wavelength Switching”
S. Tsuji, Hitachi Ltd., Japan

Area 8

Advanced Material Synthesis and Crystal Growth Technology

“InAs/In(Ga,Al)AsSb Quantum Dot Heterostructures for Photonic Devices”
J. I. Chyi, National Central Univ., Taiwan

“Present Status and Future Issues of III-V Semiconductor Nanowires”
K. Hiruma, Hitachi Ltd., Japan

“Bottom-up approach for the nanopatterning of Si(001)”
R. Koch, Johannes Kepler Uni., Austria

“In-situ X-ray diffraction during Semiconductor Nanostructure Growth”
M. Takahasi, Japan Atomic Energy Agency, Japan

Area 9

Physics and Applications of Novel Functional Materials and Devices

“3D Stacked Nanowires CMOS Integration with a Damascene Finfet Process”
T. Ernst, CEA-LETI, France

“Nanopatterned epitaxial graphene for nanoelectronics”
W. A. de Heer, Georgia Institute of Tech., USA

“Scanning Probe Measurements on Semiconductor Nanostructures”
T. Ihn, ETH Zurich, Switzerland