Awards

There are three categories of awards for authors who presented distinguished papers at SSDM.

SSDM Award

The SSDM Award is awarded to authors who contributed an outstanding paper at past SSDM.

This paper proposed the first MONOS nonvolatile semiconductor device and demonstrated its outstanding properties. The proposed structure reduced program voltage and increased speed and realized a memory device offering outstanding reliability, which opened the way for multi-layered flash memory in recent years. This structure is a core technology of 3D NAND memory, today's dominant storage memory, and supports larger capacities.

Nonvolatile memory using MOSFET was devised soon after MOSFET was developed in the 1960s. It is the main device supporting today's semiconductor industry. While floating-gate and charge-trapping mechanisms both originated at about the same time, they have been miniaturized and highly integrated in applications for different purposes. This paper focuses on a charge-trapping device that uses tunneling to a charge trap particular in the silicon nitride film to inject and hold the electron charge. Because the charge trap held the charge, the device, in principle, did not leak charge due to degradation of the insulating film in contrast to the floating-gate type, making it very reliable. Nevertheless, issues were faced in the significant property dispersion due to the use of traps scattered in the film as well as the difficulty of ascertaining device characteristics due to injected charge being discretely held in the nitride film. This paper proposed an additional ultrathin silicon oxide layer on top of the electron trap film. It became clear that this simple improvement greatly reduced the required amount of injected charge by keeping the charge trap away from the gate electrode, and this had profound effect on improving programming characteristics and retention characteristics.

Ever since the advent of NAND Flash memory, the floating gate had driven miniaturization, sweeping the market for large-capacity memory due to the simplicity of its memory operation and structure. However, around 2010, planar miniaturization, which had supported greater and greater capacities, reached its limit and 3D integration was needed. It was then that the MONOS memory device technology that this paper proposed once again came to the forefront on account of the advantage it offered of forming memory just by depositing insulator films, thereby paving the way for the creation of 3D nonvolatile memory.

For these reasons, this paper led to the realization of large-capacity storage memory, the core of today's semiconductor industry, and made a tremendous contribution to academic knowledge as well. This SSDM Award is presented in honor of those achievements.

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  Eiichi Suzuki

  (ex) National Institute of Advanced Science and Technology (AIST)

  Eiichi Suzuki received the M.S., and Ph.D. degrees in Electronic Engineering from the University of Tokyo, Tokyo, Japan in 1972 and 1983, respectively. In 1972, he joined the Electrotechnical Laboratory (ETL), Ibaraki, Japan, where he was engaged in research and development of nonvolatile semiconductor memories, solar cells, quantum functional devices, and short-channel MOS devices. From 1985 to 1986, he was a Visiting Faculty Associate with the Department of Electrical Engineering, Arizona State University, Tempe, USA and worked on the characterization of a nonvolatile semiconductor memory. In April 2001, he joined the Nanoelectronics Research Institute (NeRI), National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan, with the reorganization of ETL, and assumed the deputy Director of NeRI. Dr.Suzuki received the Ohm Technology Award in 1996. He is a fellow of the Japan Society of Applied Physics, and a member of the Institute of Electronics, Information and Communication Engineers of Japan.

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  Yutaka Hayashi

  (ex) Toyota Technological Institute (contract temporally expired)

  Dr. Yutaka Hayashi joined Electrotechnical Laboratory (ETL) in 1964. There, he developed various early phase semiconductor devices; a tunnel source MOS transistor in 1965, Schottky TTL from 1967, VMOS and DMOS in 1969, 1 nsec DSA-ED logic in 1970, CHE injection FG memories from 1971.
  
  In 1971-72, at Stanford University he worked on ultrasonic blood flow meters and developed silicon through-hole substrate technology for 3D integration.
  
  On return to ETL, he joined "Sun-Shine Project" serving NEDO committees on solar cells up to 1992 and developed advanced solar cell technologies, e.g. thin (tens of µm) cSi solar cells, hetero junction cSi solar cells, etc. Meanwhile, in 1980~1992, he initiated the development of an early phase finFET, nanosheet FETs and MONOS memory as the future scaling-durable devices.
  
  In 1992, he joined Sony Corp. and supervised the development of 0.25 to 0.18 µm MOSLSI technologies as the director of ULSI Research Laboratory, then served as a vice-president (for R&D) of Sony Semiconductor Company up to 1998.
  
  After joining in an US venture (Halo LSI) in 1999, he was invited by AIST, Tsukuba in 2004 as an invited senior research fellow and developed new nano devices (e.g. columnar nano-memory: USP2010/0208522), until 2015.
  
  He had been also a part time lecturer and then a project advisor of University of Tsukuba from 1981 to 2015 and an invited researcher of Osaka University from 2010 to 2017. He has been an invited fellow of Toyota Technological Institute from 2012 to 2023.

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  Kenichi Ishii

  (ex) Nanoelectronics Research Institute of AIST

  Kenichi Ishii joined Electrotechnical Laboratory (ETL, later National Institute of AIST) in 1964.
  He engaged in the development of basic processing technologies for silicon devices including CVD technologies for SiNx and Si thin films, and sold phase lateral epitaxy for thin bodies of early phase nanosheet FETs. Further, he worked for photolithography technologies up to excimer laser stepper technology. During the above technological development, he had made technical contributions in the development of various new MOS devices; finFETs, MONOS memories and nanosheet FETs in ETL and in AIST.
  He passed away in 2009 while travelling in Hokkaido, Japan.

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  Hisato Hiraishi

  (ex) Citizen Watch Co.,Ltd.

  Hisato Hiraishi received Ph.D. degree in physical chemistry from the University of Tokyo in 1979. Since 1979 he worked for Citizen Watch and in 1980, sent by Citizen, joined the R&D group of the MONOS memory in the Electrotechnical Laboratory. In 1981 he returned Citizen and had been engaged in development of liquid crystal display, inkjet printer and new technologies for watch at the Technical Laboratory of the company. In 2000 he assumed the head of the Laboratory and then became a director of Citizen in 2003. After 2007 he took his position at two subsidiary companies; a managing director of Citizen Electronics and the president &CEO of Citizen Systems.

SSDM Paper Award (PA)

SSDM Paper Award is awarded to the best paper presented at the last SSDM.

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  Goutham Arutchelvan

  imec

  Goutham Arutchelvan obtained his Master's degree in Microelectronics Engineering from TU Delft, Netherlands, in 2014. He completed his PhD in Materials Science at KU Leuven in 2021, where he collaborated with imec to research contacts to semiconducting transition metal dichalcogenides. Between 2019 and 2022, Goutham worked as a researcher at imec, concentrating on Si-based CMOS and beyond CMOS devices. He was involved in exploring backside power delivery for Si-FinFET technologies and modeling thin film transistors like IGZO for back-end functionality. Goutham has co-authored 40 papers and has been a reviewer for numerous journals, such as Nature Nanotechnology, ACS Electronic Materials, Applied Physics Letters, IEEE Transactions on Electron Devices. Currently, he works as the Principal Engineer at TSMC's Corporate Research in Taiwan, where he is interested in exploring new channel materials for front-end and back-end logic.

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  Thomas Chiarella

  imec

  T. Chiarella received the M. Sc. Degree in Electronics from the "Institut Supérieur Industriel Catholique du Hainaut" in Charleroi, Belgium in 2002. He directly joined the Silicon Process & Device Technology division of imec as Characterization Engineer and took part, as Device Engineer, in technology transfers (130nm, 90nm, 65nm, 14nm) and the baseline yield improvement. He takes part in imec's Affiliation Program focusing on successful and efficient definition and evaluation of finFET, nanosheet and CFET technologies. He is now Senior Researcher in charge of finFET and CFET device design. He has actively contributed to the Horizon 2020 ASCENT EU project (Project no. 654384). In addition to own publications in ICMTS/ESSDERC proceedings and Solid-State Electronics journal, he contributed to more than 50 technical papers (mainly IEDM/VLSI).

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  Hiroaki Arimura

  imec

  Hiroaki Arimura is a principal member of technical staff at imec, Belgium. He received M.S. and Ph.D. degrees in engineering from Osaka University, Japan, in 2009 and 2011, respectively. In 2011, he joined imec, Belgium, as a postdoctoral researcher and studied NBTI reliability of ultra-thin EOT devices. He became a researcher of imec in 2013 and engaged in a development of metal / high-k gate stack on high-mobility channel materials such as Ge and SiGe, and conducted device studies including FinFET and Gate-All-Around nanowire transistors. Currently, he is leading the gate stack module development for advanced logic and memory peripheral devices.

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  Anabela Veloso

  imec

  Anabela Veloso received a Ph.D. from INESC-IST-Lisbon University, Portugal in 2002. Since 2001, she has been working at Imec, in Leuven, Belgium, where she is a principal member of technical staff. Currently, her main research interests are in the areas of advanced CMOS device physics, integration, characterization, and technology, with recent focus on the exploration of scaled nanowires/nanosheets based FETs (with lateral or vertical transport), logic with functional backside, buried power rails, nTSVs, and overall novel device schemes while also taking into consideration possible new options for transistor engineering and connectivity from the wafer’s front/backside. She has authored or co-authored more than 200 papers published in peer-reviewed international conference proceedings and technical journals, presented 20 invited conference talks, and has been (co-)inventor of more than 23 filed/granted patents. She has also been serving in several conference committees including IEDM, SSDM, ECS Meeting, and the Symposium on VLSI Technology and Circuits.

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  Anne Jourdain

  imec

  Anne Jourdain received her PhD degree in Physics from University Joseph Fourier of Grenoble, France, in 1998. In 1999, she joined IMEC (Interuniversity Microelectronics Center) in Leuven, Belgium, to work on wafer-level-packaging solutions for RF-MEMS applications. In 2007, she joined the 3D Integration Research Program of IMEC to work on various wafer-to-wafer bonding and wafer thinning technologies. In 2019, she became responsible for the Backside Power Delivery Network integration activities within the program before taking the lead of the 3D Heterogeneous Integration team in 2022, looking at collective die-to-wafer and direct hybrid bonding technologies for 3D stacking applications.

• Eugenio Dentoni Litta

  imec

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  Naoto Horiguchi

  imec

  Naoto Horiguchi is the director of CMOS device program in imec, Leuven, Belgium. He started his carrier in semiconductor device R&D in Fujitsu Laboratories Ltd. in 1992. In 1992-1999, he was engaged in device R&D by using semiconductor nano structures in Fujitsu laboratories Ltd. and University of California, Santa Barbara. In 2000-2006, he was engaged in 90-45nm CMOS technology development in Fujitsu Ltd. From 2006, he is with imec, Leuven, Belgium, where he is engaged in advanced CMOS device R&D together with worldwide industrial partners, universities, and research institutes. His current focus is CMOS device scaling for 10Å technology node and beyond.

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  Jérôme Mitard

  imec

  Jérôme Mitard received the Ph.D. degree in microelectronic engineering from the Polytechnic University School of Marseille (France), in 2003. Over three years, he acted as an STMicroelectronics assignee with CEA-LETI, Grenoble, France, where he was deeply involved in the electrical characterization and reliability of hafnium-based dielectric stacks with replacement metal gate targeting sub-45nm node complementary metal–oxide–semiconductor (CMOS) logic technologies. After his Ph.D. in microelectronics at INPG, France, he joined the R&D center IMEC, Leuven, Belgium, as a device researcher, working on the experimental demonstration of the germanium-based high-mobility channels in planar, Fin and GAA FET architectures. He also technically led the development of the IGZO-based transistors fueling the active BEOL and DRAM roadmaps. In parallel, he joined the staff management team, first as a team leader of the compute device research and now expanding his leadership role toward quantum devices as a R&D device manager in imec.

SSDM Best Student Award (BSA)

SSDM Best Student Award is awarded to the best student paper presented at the last SSDM. This award was established from SSDM 2022.

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  Chia-Tsong Chen

  The University of Tokyo

  Chia-Tsong Chen received the B.E. and M.E. degree in electronics engineering from the National Chiao Tung University, Hsinchu, Taiwan in 2016 and 2019 respectively. He received Ph.D. degree in the Department of Electrical Engineering and Information Systems, School of Engineering from the University of Tokyo in 2022 under the supervision of Prof. Shinichi Takagi. After his Ph.D., he joined the University of Tokyo as a post-doctoral researcher with the aim to investigate the impact of performance enhancement through strain engineering in extremely-thin body (Si)Ge channels. Since April 2023, he has been working as a researcher in Device Technology Research Institute in National Institute of Advanced Industrial Science and Technology (AIST) for advanced device process research. His research interest includes the advanced technology and innovations for future CMOS devices, such as high mobility material for extremely-thin body channel, 3D heterogeneous integration, and ferroelectric HfO2-based materials for gate stack and memory applications.