History of SSDM Paper Award

Year of Award Year of presentaion Presentation number Paper Title Authors Affiliation (Country)
SSDM2022
54th
2021 A-1-02 16×8 Quantum Dot Array Operation at Cryogenic Temperatures Noriyuki Lee1, Ryuta Tsuchiya1, Yusuke Kanno1, Toshiyuki Mine1, Yoshitaka Sasago1, Go Shinkai1, Raisei Mizokuchi2, Jun Yoneda2, Tetsuo Kodera2, Chihiro Yoshimura1, Shinichi Saito1, Digh Hisamoto1 and Hiroyuki Mizuno1 1 Hitachi, Ltd. (Japan), 2 Tokyo Tech (Japan),
SSDM2021
53rd
2020 I-5-02 TiN/MgO/Si memrisitive devices as a selectorless synapse for ultralow-power analog neuron chip and time-series applications Takao Marukame1, Koichi Mizushima1, Kumiko Nomura1, Junichi Sugino2, Toshimitsu Kitamura2, Koji Takahashi2, Yutaka Tamura2, and Yoshifumi Nishi1 1 Toshiba Corporation, 2 Toshiba Information Systems (Japan) Corporation
SSDM2020
52nd
2019 K-1-02 Demonstration of 1200 V / 1.4 mΩ cm2 Vertical GaN Planar MOSFET Fabricated by All Ion Implantation Process Ryo Tanaka1, Shinya Takashima1, Katsunori Ueno1, Hideaki Matsuyama1, Yuta Fukushima1, Masaharu Edo1, and Kiyokazu Nakagawa2 1 Fuji Electric Co., Ltd., 2 Univ. of Yamanashi
SSDM2018
50th
2017 F-3-04 Ultra-sensitive biosensor with capacitive coupling-gate InGaZnO-based FET K. Ito1, K. Nishimura1, K. Ikeda2, K. Matsuzawa2, T. Tezuka2, T. Sakata1 1.Univ. of Tokyo (Japan), 2.Toshiba Corp. (Japan)
SSDM2017
49th
2016 C-3-02 1.3µm Hybrid III-V on Silicon Transmitter Operating at 25Gb/s T.Ferrotti1,2,3, B.Blampey1, H.Duprez1, C.Jany1, A.Chantre2, ○F.Boeuf2, C.Seassal3, B.Ben Bakir1 1.Univ. Grenoble Alpes, CEA, LETI, MINATEC Campus (France), 2.STMicroelectronics (France), 3.Univ. de Lyon (France)
SSDM2016
48th
2015 K-2-4 Steep-Slope Tunnel FET using InGaAs-InP Core-Shell Nanowire/Si Heterojunction K. Tomioka1, 2, F. Ishizaka1, J. Motohisa1, T. Fukui1 1.Hokkaido Univ., 2.JST-PRESTO, Japan
SSDM2015
47th
2014 F-1-2 Operations of CMOS Inverter and Ring Oscillator Composed of Ultra-Thin Body Poly-Ge p- and n-MISFETs for Stacked Channel 3D-IC Y. Kamata1, M. Koike1, E. Kurosawa1, M. Kurosawa2, H. Ota1, O. Nakatsuka2, S. Zaima2 and T. Tezuka1 1.AIST, 2.Nagoya Univ.
SSDM2014
46th
2013 B-1-2 Thermal and Plasma Treatments for Improved (Sub-)1nm EOT Planar and FinFET-based RMG High-k Last Devices and Enabling a Simplified Scalable CMOS Integration Scheme A. Veloso1, G. Boccardi1, L.Å. Ragnarsson1, Y. Higuchi2, H. Arimura1,3, J.W. Lee1,3, E. Simoen1, M.J. Cho1, Ph.J. Roussel1, V. Paraschiv1, X. Shi1, T. Schram1, S.A. Chew1, S. Brus1, A. Dangol1, E. Vecchio1, F. Sebaai1, K. Kellens1, N. Heylen1, K. Devriendt1, H. Dekkers1, A. Van Ammel1, T. Witters1, T. Conard1, I. Vaesen1, O. Richard1, H. Bender1, R. Athimulam1, T. Chiarella1, A. Thean1 and N. Horiguchi1 1.Imec, 2.Panasonic, 3.K. U. Leuven
SSDM2013
45th
2012 J-5-2 Eight-bit CPU with Nonvolatile Registers Capable of Holding Data for 40 Days at 85°C Using Crystalline In-Ga-Zn Oxide Thin Film Transistors T. Ohmaru, S. Yoneda, T. Nishijima, E. Masami, H. Dembo, M. Fujita, H. Kobayashi, K. Ohshima, T. Atsumi, Y. Shionoiri, K. Kato, Y. Maehashi, J. Koyama and S. Yamazaki Semiconductor Energy Lab. Corp. Ltd., Japan
SSDM2012
44th
2011 F-1-2 Studies on Static Noise Margin and Scalability for Low-Power and High-Density Nonvolatile SRAM using Spin-Transfer-Torque (STT) MTJs T. Ohsawa, F. Iga, S. Ikeda, T. Hanyu, H. Ohno and T. Endoh Tohoku Univ., Japan
SSDM2011
43rd
2010 D-5-4L Stimulated Emission in Silicon Fin Light-Emitting Diode S. Saito1,3, K. Tani1,3, T. Takahama1, M. Takahashi1, E. Nomoto1, Y. Matsuoka1, J. Yamamoto1, Y. Suwa2,3, D. Hisamoto1, S. Kimura1, H. Arimoto1, T. Sugawara1, M. Aoki1, K. Torii1 and T. Ido1,3 1.Hitachi, Ltd., Central Res. Lab., 2.Hitachi Advanced Res. Lab., 3.PECST, Japan
SSDM2010
42nd
2009 K-4-3 Carrier-induced Dynamic Backaction in GaAs Micromechanical Resonators H. Okamoto1, D. Ito1,2, K. Onomitsu1, H. Sanada1, H. Gotoh1, T. Sogawa1 and H. Yamaguchi1,2 1.NTT Basic Res. Labs., 2.Tohoku Univ., Japan
SSDM2009
41st
2008 B-1-3 High Mobility sub-60nm Gate Length Germanium-On-Insulator Channel pMOSFETs with Metal Source/Drain and TaN MIPS Gate K. Ikeda1, Y. Yamashita1, M. Harada1, T. Yamamoto1, S. Nakaharai1, N. Hirashita1, Y. Moriyama1, T. Tezuka1, N. Taoka2, I. Watanabe3, N. Hirose3, N. Sugiyama1 and S. Takagi2,4 1.MIRAI-ASET, 2.MIRAI-ASRC, 3.NICT, 4.Univ. of Tokyo, Japan
SSDM2008
40th
2007 A-3-4 nMOSFET Reliability Improvement attributed to the Interfacial Dipole formed by La Incorporation in HfO2 C. Y. Kang1, P. Kirsch2, D. Heh1, C. Young1, P. Sivasubramani1, G. Bersuker1, S. C. Song1, R. Choi1, B. H. Lee2, J. Lichtenwalner3, J. S. Jur3, A. I. Kingon3, and R. Jammy2 1.SEMATECH, USA, 2.IBM Assignee, USA, 3.North Carolina State Univ., USA


D-8-5 Fabrication of single electron transistor using cage-shaped protein supramolecule S. Kumagai1, S. Yoshii1, N. Matsukawa1, R. Tsukamoto3, K. Nishio1, and I. Yamashita1,2,3 1.Matsushita Electric Industrial Co., Ltd., Japan, 2.NAIST, Japan, 3.Core Research for Evolutional Sci. and Tech., Japan
SSDM2007
39th
2006 A-2-2 Optical Properties of Dynamically-Modulated Dots and Wires Formed by Surface Acoustic Waves T. Sogawa1, H. Gotoh1, Y. Hirayama1, T. Saku1, S. Miyashita2, P. V. Santos3, and K. H. Ploog3 1.NTT Basic Research Labs., Japan, 2.NTT Advanced Technology Corp., Japan, 3.Paul Drude Institute, Germany
SSDM2006
38th
2005 A-1-3 Extendibility of High Mobility HfSiON Gate Dielectrics S. Inumiya, T. Miura, K. Shirai, T. Matsuki, K. Torii* and Y. Nara Semiconductor Leading Edge Technologies, Inc., Japan


I-1-2 High-Voltage 4H-SiC RESURF MOSFETs Processed by Oxide Deposition and N2O Annealing T. Kimoto, H. Kawano, M. Noborio and J. Suda Kyoto University, Japan
SSDM2005
37th
2004 H-7-4 Observation of Light Emission at 〜1.5 µm from InAs Quantum Dots in Photonic Crystal Microcavity S. Iwamoto, J. Tatebayashi, T. Fukuda, T. Nakaoka, S. Ishida and Y. Arakawa University of Tokyo, Japan


C-10-1 Dielectric Constant Increase of Yttrium-Doped HfO2 by Structural Phase Modification K. Kita, K. Kyuno and A. Toriumi University of Tokyo, Japan
SSDM2004
36th
2003 F-9-2 100-Gbit/s Full-Rate Operation of PD-EAM Optical Gate for Retiming Function T. Yoshimatsu, S. Kodama, K. Yoshino and H. Ito NTT Corp., Japan