History of SSDM Award

Year of the awardAwarded thesis
Conference number heldYear of presentaionThesis numberName of awardeesTitle of thesis
29th
(2018)
26th1994 Tadashi Shibata, Hideo Kosaka, Hiroshi Ishii, and Tadahiro Ohmi
Tohoku University
A Neuron-MOS Neural Network Using Low-Power Self-Learning-Compatible Synapse Cells
28th
(2017)
25th1993D-9-4 Takatomo Enoki, Yohtaro Umeda and Yasunobu Ishii
NTT LSI Laboratories
0.05-µm-Gate InAlAs/InGaAs HEMT and Reduction of Its Short-Channel Effects
27th
(2016)
11th1979B-3-4 S. Arai, Y. Itaya, Y. Suematsu and K. Kishino
Tokyo Institute of Technology
1.5-1.6 µm Wavelength (100) GaInAsP/InP DH Lasers
26th
(2015)
19th1987C-3-6 H. Shinriki, Y. Nishioka and K. Mukai
Central Research Laboratory Hitachi Ltd.
Highly Reliable Ta2O5/SiO2 Double Dielectric Films on Poly Crystalline Silicon
25th
(2014)
24th1992S-IV-3 A.Toriumi, T. Mizuno, M. Iwase, M. Takahashi, H. Niiyama, M. Fukumoto, S. Inaba, I. Mori, and M. Yoshimi
ULSI Research Center, Toshiba Corporation
High Speed 0.1µm CMOS Devices Operating at Room Temperature
24th
(2013)
9th1977C-1-1 H. Suzuki, K. Suyama, K. Odani, and M. Fukuta
Fujitsu Laboratories Ltd.
C-band 10W Power GaAs MESFET with an Internal Matching Circuit

9th1977C-1-2 Y. Aono, A. Higashisaka, T. Ogawa and F. Hasegawa
Central Research Laboratories, Nippon Electric Co. Ltd.
X- and Ku-band Performance of Submicron Gate GaAs Power FETs
23rd
(2012)
13th1981A-3-8 I. Kato, T. Ito, S. Inoue, T. Nakamura, and H. Ishikawa
Fujitsu Laboratories Ltd.
Ammonia annealed SiO2 films for thin gate insulator
22nd
(2011)
17th1985C-3-9
LN
T. Sekigawa, Y. Hayashi*, K. Ishii**, and S. Fujita***
Nanoelectronics Research Institute of AIST, *Nanosystem Research Institute of AIST, **(Ex) Nanoelectronics Research Institute of AIST, ***Corporate Technology Planning Center, Ricoh Company, Ltd.
XMOS Transistor for a 3D-IC
21st
(2010)
18th1986A-7-4 K. Yamada
Univ. of Tsukuba
Thermodynamical Approach to a New High Dielectric Capacitor Structure: W/HfO2/W
20th
(2009)
25th1993PB-3-9 K. Natori
Univ. of Tsukuba
Ⅰ-Ⅴ Characteristics of SOI MOSFETs in Ballistic Mode
19th
(2008)
2nd19701-1 S. Furukawa and H. Ishiwara
Tokyo Tech.
Vacancy Distribution Theory for Ion-Implanted Target
18th
(2007)
3rd19715-2 H. Sakaki and T. Sugano
Univ. of Tokyo
Anistropic Channel Conductivity of a MOS Transistor on the (110) Surface of Silicon
17th
(2006)
14th1982B-2-3 H. Soda, Y. Motegi, and K. Iga
Tokyo Tech.
Threshold Condition and Design of Surface Emitting GaInAsP/InP Injection Lasers
16th
(2005)
19th1987C-4-2 H. Matsunami, N. Kuroda, W. S. Yoo, S. Nishino, and K. Shibahara
Kyoto Univ., Japan
Step-Controlled VPE Growth of SiC Single Crystals at Low Temperatures
15th
(2004)
22th1990S-CII-4 Y. Hayashide, H. Miyatake, J. Mitsuhashi, M. Hirayama, T. Higaki, and H. Abe
Mitsubishi Electric, Japan
Fabrication of Storage Capacitance-Enhanced Capacitors with a Rough Electrode

22th1990S-CII-5 H. Watanabe, N. Aoto, S. Adachi, T. Ishijima, E. Ikawa, and K. Terada
NEC, Japan
A New Stacked Capacitor Structure using Hemispherical-Grain(HSG) Poly-Silicon Electrodes
14th
(2003)
24th1992S-1-1 I. Akasaki and H. Amano
Meijo Univ., Japan
Room Temperature Ultraviolet/Blue Light Emitting Devices Based on AlGaN/GaN Multi-Layered Structure
13th
(2002)
3th19715-5 H. Hara, T. Sato, Y. Takeishi, K. Ohuchi, H. Tango, Y. Ohmori, H. Iizuka, Y. Yasuda, and F. Masuoka
Toshiba Research and Development Center, Japan
Avalanche-Injection MOS Read-Only Memory
12th
(2001)
6th1974B-3-3 M. Esashi and T. Matsuo
Tohoku Univ., Japan
Biomedical Cation Sensor Using Field Effect of Semiconductor
11th
(2000)
4th19726-1 T. Warabisako, I. Yoshida, and T. Tokuyama
Hitachi, Japan
Properties of MOS Structures Prepared on Substrates Having Ion-Implanted Impurity Distribution Profile
9th
(1998)
12th1980C-3-9
(LN)
T. Mimura, S. Hiyamizu, H. Hashimoto, and H. Ishikawa
Fujitsu Labs., Japan
An Enhancement-Mode High Electron Mobility Transistor for VLSI
10th
(1999)
6th1974B-2-1 H. Abe
Mitsubishi, Japan
The Application of Gas Plasma to the Fabrication of MOS LSI (Invited)

18th1986B-8-4 Y. Matsushita, M. Wakatsuki, and Y. Saito
Toshiba, Japan
Improvement of Silicon Surface Quality by H2 Anneal
8th
(1997)
12th1980A-4-7 T. Sakai, Y. Kobayashi, H. Yamauchi, M. Sato, and T. Makino
NTT, Japan
High Speed Bipolar ICs Using Super Self-Aligned Process Technology
7th
(1996)
11th1979A-3-7 K. Izumi, M. Dohken, and H. Ariyoshi
NTT, Japan
High Speed C-MOS IC Using Buried SiO2 Layers Formed by Ion Implantation
6th
(1995)
5th19733-4 H. Yonezu, I. Sakuma, T. Kamejima, M. Ueno, K. Kobayashi, K. Nishida, Y. Nannichi, and I. Hayashi
Nippon Electric, Japan
Degradation of AlxGa1-xAs Double Heterostructure Lasers
5th
(1994)
10th1978A-1-4 M. Koyanagi and N. Hashimoto
Hitachi, Japan
Novel High Density, Stacked Capacitor MOS RAM
4th
(1993)
7th1975A-1-1 Y. Horiike and M. Shibagaki
Toshiba, Japan
A New Chemical Dry Etching
3rd
(1992)
11th1979C-3-4 M. Tajima, A. Yusa*, and T. Abe**
ETL, *Komatsu Electronic Metals and **Shin-Etsu Handotai, Japan
Characterization of Residual Impurities in Highly Pure Si Crystals by Photoluminescence Technique
2nd
(1991)
6th1974A-1-1 T. Tsukada
Hitachi, Japan
Buried-Heterostructure Injection Lasers
1st
(1990)
1st19694-1 Y. Tarui, Y. Hayashi, and T. Sekigawa
ETL, Japan
Diffusion Self-Aligned MOST: A New Approach for High Speed Device
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